1. Field of the Invention
The present invention relates to a frequency locking structure, and more particularly to a frequency locking structure applied to phase-locked loops.
2. Background of the Related Art
Phase-locked loops (PLL) are generally used in the recovery of data and clock, modulation and demodulation of frequency and phase, and generation of stable and multiple clock. For the design of signal-mixing integrated circuits and system-on-chip (SOC), the phase-locked loops are necessary for the variable application requirement. Generally, there are specifications to be tested for the PLLs: lock-in range, lock-in time, and jitter.
The PLLs are capable of generating clean and stable clocks. However, the stability of the clocks may be deteriorated by noises and estimated by measuring the jitter outputted from the PLLs. FIG. 1 is a block diagram illustrating a conventional PLL. An input signal (f_in) is processed by a divider 12 (M) to output a reference input signal (ref_in). An oscillator output signal (Vco_out) feedbacked by a PLL 10 is processed by a divider 16 (N) to output a feedback signal (Vco_in). The reference input signal (ref_in) and the oscillator output signal (Vco_out) are inputted into the PLL 10 to generate an output signal. The output signal is processed by a divider 14 (P) to output a frequency output signal (f_out). These relationships may be expressed by the following formula (1):f_out=f_in*N/(M*P)  (1)wherein (N/(M*P)) is simplified to be a simple integer. Generally, the jitter from the PLL is derived from the design of the PLL 10, the reference input signal (ref_in) from the divider 12 and the jitter of the feedback signal (Vco_out) from the divider 16.
Accordingly, f_out is acquired by the formula (2) in condition that (f_in) is 1 KHz and (f_out) is 12 MKHz as follows:f_out=12 MKHz=1K*N/(M*P)
For example, M is 1 and P is 1 in the formula (2) to acquire N=12000. In the case, the reference input signal (ref_in) and the feedback signal (Vco_in) are identical, and f_in/M is 1K. Thus, the reference input signal (ref_in) and the feedback signal (Vco_in) are 1K, respectively. That is, (f_out) is 12 MKHZ in conditions of ref_in =Vco_in =1K, M=P=1, and N=12000. The clock input of each (f_in) should generate the 1200 frequency output of (Lout). (Vco_in) and (ref_in) are identical in condition that N should be 12000. However, when the signal jitter of (f_in) is very high and the difference between (ref_in) and (Vco_out) is large, the clock jitter of (Vco_out) correspondingly increases.